Event counter in verilog -

i'm verilog beginner, i'm try write "event counter" on verilog.... code, work "period" set 16'b0000000000000001, if try set period 16'b0000000000001000, result(out_event) '0'. can me fix ?

module mymodule(     input  wire          clk,     input  wire             enable,     input  wire             reset,      input    wire [15:0]        period,     input    wire              in_event,      output reg                  out_event             );  reg en = 1'b0;  reg re = 1'b0; reg [15:0] count = 16'b0000000000000000; @(posedge clk) en <= enable; @(posedge clk) re <= reset;   @(in_event)begin   if(in_event == 1'b1)begin if(re)begin     count <= 0 ;      out_event <= 1'b0; end else begin     if(en) begin         if(count == period-1)begin             out_event <= 1'b1;             count <= 0;         end else begin             count <=count + 1;             out_event <= 1'b0;         end     end else begin         out_event <= 1'b0;     end end  end else begin     out_event <= 1'b0;  end  end   endmodule 

thanks in advance

the counter counts number of posedge of in_event wire. so, can use @(posedge in_event)?

i simulated code, providing testbench it.

i not have knowledge hardware synthesis, personally, suggest write logic based on edge/level of clock.

this code works well. have @ link.

you can configure various values of period in testbench, hope helpful.