assembly - x86 32 bit opcodes that differ in x86-x64 or entirely removed -
i've looked wikipedia x86 backward compatibility in x86-x64 , says:
x86-64 backwards compatible 16-bit , 32-bit x86 code.because full x86 16-bit , 32-bit instruction sets remain implemented in hardware without intervening emulation, existing x86 executables run no compatibility or performance penalties,whereas existing applications recoded take advantage of new features of processor design may achieve performance improvements.
so i've tested instructions see yield entirely different opcodes (rather applying prefix) such as: inc/dec. looking @ (x86):
\x40 inc eax
\x48 dec eax
and while assembling same in x86-x64 yields:
\xff \xc0 inc eax
\xff \xc8 dec eax
i'm trying figure out reason , more examples of other instructions has same symptoms yield different opcodes. familiar push, pop, call, ret, enter , leave not available 32 bit in x86-x64.
the instructions entirely removed obscure obsolete ones, binary-coded-decimal stuff , aam (ascii-adjust after multiplication) fixing binary-coded-decimal after doing normal binary add/sub/mul/div.
however, encodings of instructions removed: in case, 32bit can use inc r32
single-byte opcodes (0x40 + register-number). 64bit mode has inc r/m32
encoding, register incremented specified 2nd byte. (in case, 0x4x bytes repurposed rex prefix byte).
intel's insn reference (follow link in https://stackoverflow.com/tags/x86/info) shows following inc
:
opcode instruction op/ 64-bit compat/ en mode leg mode ff /0 inc r/m32 m valid valid increment r/m doubleword 1. 40+ rd inc r32 o n.e. valid increment doubleword register 1.
n.e. means not encodable.
the op/en column describes how operands encoded.
jan hubicka's amd64 isa overview briefly describes repurposing of single-byte inc/dec opcodes rex prefixes, , default operand sizes , how immediate data still 32bit. movabs
available loading 64bit immediate constants, or load/store from/to 64bit absolute address.
amd's amd64 manual, section 2.5.11 reassigned opcodes has table quite short. lists:
4x inc/dec r32
turned rex prefixes63 arpl
becamemovsxd
(sign-extend dword qword, when used rex.w=1 (which means w bit in rex prefix = 1)).
early amd64 , intel emt64 cpus left out sahf/lahf
in long mode, later re-added instruction same opcode in 32bit. table doesn't list instructions removed entirely (the bcd instructions , maybe others) removed make room possible future extensions.
they have simplified things lot, , made x86-64 better cleaner instruction set more room future extensions, every difference 32bit means more decoder transistors. there no machine instructions moved different opcode in 64bit.
multiple machine instructions share same asm mnemonic, mov
being overloaded one. there loads, stores, mov immediate-constants, move to/from segment registers, in 8bit , 32bit. (16bit 32bit operand-size prefix, same 64bit rex prefix.) there's sepecial opcode loading rax 64bit absolute address. there's special opcode loading 64bit immediate-constant register. (at&t syntax calls movabs, it's still mov in intel/nasm)
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