exception - ARM interrupts and context saving -


i trying understand how interrupts work in arm architecture(arm7tdmi specific). know there 7 exceptions (reset,data abort, fiq, irq, pre-fetch abort, swi , undefined instruction) , execute in particular modes(supervisor, abort, fiq, irq, abort, supervisor , undefined respectively). have following questions.

1. when , f bits in cpsr(status register) set 1 disable external , fast interrupt, other 5 exceptions disabled ?

2. if swi not disabled when , f bits enabled then, possible intentionally trigger swi exception within isr of external interrupt?

3.when interrupt triggered saving cpsr spsr, changing mode done processor itself. so, enough write isr handler function , update vector table handler addresses(i don't want save r0 r12 general purpose registers) ?

4. whenever mode of execution changed context saving happens internally processor(even when change mode manually)?

5. how mask/disable swi exception?


thank you.

  1. when , f bits in cpsr(status register) set 1 disable external , fast interrupt, other 5 exceptions disabled ?

no, these depend on code correct. instance, compiler not generate swi instruction.

  1. if swi not disabled when , f bits enabled then, possible intentionally trigger swi exception within isr of external interrupt?

yes, possible. may check mode of spsr in swi handler , abort (or whatever appropriate) if want.

3.when interrupt triggered saving cpsr spsr, changing mode done processor itself. so, enough write isr handler function , update vector table handler addresses(i don't want save r0 r12 general purpose registers) ?

no 1 wants save registers. however, if use r0 r12 main code become corrupt. banked sp made store these registers. also, vector table not handler address instruction/code.

  1. whenever mode of execution changed context saving happens internally processor(even when change mode manually)?

no, instruction/code in vector page responsible saving context. if have pre-emptable os need save context process , restore later. may have 1000s of processes. cpu not automatically. context save area may rooted in super mode stack; can use isr/fiq sp temporary register in case. instance, switch_to function in arm linux maybe helpful. thread_info rooted in supervisor stack kernel management of user space process/thread. minimum code (with features removed) is,

__switch_to:     add ip, r1, #ti_cpu_save                @ save area `ip`.     stmia   ip!, {r4 - sl, fp, sp, lr} )    @ store regs on stack     add r4, r2, #ti_cpu_save                @ restore area `r4`     ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ load regs saved     @ note last instruction returns previous      @ switch_to call destination thread/process
  1. how mask/disable swi exception?

you can not this. write swi handler nothing increment pc and/or jump undefined handler depending on does.


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